This paper presents a new heuristic, concurrent, iterative loop based scheduling and allocation algorithm for high-level synthesis of digital signal processing (DSP) architectures using heterogeneous functional units. In a heterogeneous architecture, functional units could be either bit-serial or digit-serial or bit-parallel. This paper assumes a library of heterogeneous implementation style based functional units to be available. The proposed heuristic synthesis approach generates optimal and near-optimal area solutions. Although optimum synthesis of such architectures were proposed using an integer linear programming (ILP) model our method can produce similar solutions in one to two orders of magnitude less time, at the expense of sacrificing the cost optimality. This new approach has been incorporated into the Minnesota Architecture Synthesis (MARS-II) system.