Dipole Heterostructure Field-Effect Transistor

Dipole heterostructure field-effect transistors (dipole HFET's) fabricated in AIGaAs/GaAs use doped p+ + and n+ + planes in the charge control AlGaAs layer to form a dipole that provides a considerably larger barrier between the channel and the gate than that in conventional heterostructure FET's. This leads to a reduction of the forward-biased gate current in enhancement-mode n-channel devices, by a factor of approximately 9 at 1.2 V in the experimental devices, when compared with equivalent conventional HFET's. We also observe a much broader transconductance region, in the range 0.5–2.5-V gate bias, a higher maximum drain current, and no negative transconductance.