Abstract
Multiple parametric faults due to normal process variations are extremely important for analog circuits. Very few analog DFT techniques target multiple parametric faults. In this paper we present a DFT scheme that targets high performance analog circuits. In particular, are target a popular switched-capacitor based A/D converter. The DFT scheme is based on an analog-to-digital capacitor ratio converter circuit. The circuit is used to completely characterize the transfer function of a charge redistribution A/D converter. Extensive simulation results that include practical process variations are used to verify our DFT scheme.
| Original language | English (US) |
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| Title of host publication | Proceedings of the Custom Integrated Circuits Conference |
| Publisher | IEEE |
| Pages | 151-154 |
| Number of pages | 4 |
| ISBN (Print) | 0780354443 |
| State | Published - Jan 1 1999 |
| Event | Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99 - San Diego, CA, USA Duration: May 16 1999 → May 19 1999 |
Other
| Other | Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99 |
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| City | San Diego, CA, USA |
| Period | 5/16/99 → 5/19/99 |