Digital detection of parametric faults in data converters

Bapiraju Vinnakota, Ramesh Harjani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

Multiple parametric faults due to normal process variations are extremely important for analog circuits. Very few analog DFT techniques target multiple parametric faults. In this paper we present a DFT scheme that targets high performance analog circuits. In particular, are target a popular switched-capacitor based A/D converter. The DFT scheme is based on an analog-to-digital capacitor ratio converter circuit. The circuit is used to completely characterize the transfer function of a charge redistribution A/D converter. Extensive simulation results that include practical process variations are used to verify our DFT scheme.

Original languageEnglish (US)
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherIEEE
Pages151-154
Number of pages4
ISBN (Print)0780354443
StatePublished - Jan 1 1999
EventProceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99 - San Diego, CA, USA
Duration: May 16 1999May 19 1999

Other

OtherProceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99
CitySan Diego, CA, USA
Period5/16/995/19/99

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