Digital detection of analog parametric faults in SC filters

Ramesh Harjani, Bapiraju Vinnakota

Research output: Contribution to journalConference articlepeer-review

7 Scopus citations


Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration it is used in. We present a DFT scheme that offers the accuracy needed to test high-quality circuits. The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors. The circuit is used to completely characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios. In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy, and filter parameters can be shown to be satisfied to within 0.1% accuracy. A filter can be shown to satisfy all its functional specifications through this characterization process. We believe the accuracy of our scheme is at least an order of magnitude greater than that offered by any other scheme reported in the literature.

Original languageEnglish (US)
Pages (from-to)772-777
Number of pages6
JournalProceedings - Design Automation Conference
StatePublished - 1999
Event36th Annual Design Automation Conference, DAC 1999 - New Orleans, LA, USA
Duration: Jun 21 1999Jun 25 1999


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