Digital circuit design challenges and opportunities in the era of nanoscale CMOS

Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar, Kenneth L. Shepard

Research output: Contribution to journalArticlepeer-review

164 Scopus citations

Abstract

Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly unruly behavior of scaled complementary metal-oxide-semiconductor devices and the systems we seek to construct from them. As we move forward into the nanoscale regime, circuit design is burdened to ldquohiderdquo more of the problems intrinsic to deeply scaled devices. How this is being accomplished is the subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. We survey work to build accurate simulation models for nanoscale devices. We discuss the unique problems posed by nanoscale lithography and the role of geometrically regular circuits as one promising solution. Finally, we look at recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation.

Original languageEnglish (US)
Article number4403891
Pages (from-to)343-365
Number of pages23
JournalProceedings of the IEEE
Volume96
Issue number2
DOIs
StatePublished - Feb 2008
Externally publishedYes

Bibliographical note

Funding Information:
Manuscript received February 2, 2007; revised August 17, 2007. This work was supported in part by the Center for Circuit and System Solutions under the Focus Center Research Program. B. H. Calhoun is with the Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA 22904 USA (e-mail: bcalhoun@virginia.edu). Y. Cao is with the Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: yu.cao@asu.edu). X. Li, K. Mai, L. T. Pileggi, and R. A. Rutenbar are with the Department of Electrical and Computer Engineering, Carnegie–Mellon University, Pittsburgh, PA 15213 USA (e-mail: xinli@ece.cmu.edu; kenmai@ece.cmu.edu; pileggi@ece.cmu.edu; rutenbar@ece.cmu.edu). K. L. Shepard is with the Department of Electrical Engineering, Columbia University, New York, NY 10027 USA (e-mail: shepard@ee.columbia.edu).

Funding Information:
Most of the circuit examples used to illustrate ideas in this paper came from the authors’ participation in the Center for Circuit & System Solutions (C2S2),3 one of five research centers funded under the Focus Center Research Program (FCRP),4 a Semiconductor Research Corporation program. The authors are grateful to D. Radack and J. Zolper of the Defense Advanced Research Projects Agency and to S. Thomas and B. Weitzman of FCRP for their support and leadership in championing the Focus Center Research Program, in particular, their support of C2S2. They are also grateful to their many faculty and student colleagues in C2S2 for their ideas and inputs on this paper.

Keywords

  • Clock distribution
  • Complementary metal-oxide-semiconductor (CMOS)
  • Device scaling
  • Digital circuits
  • Lithography
  • Logic
  • Manufacturability
  • Memory
  • Optimization
  • Power distribution
  • Regular circuit fabrics
  • Statistical variability
  • Yield

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