Digit-serial reconfigurable FPGA logic block architecture

Research output: Contribution to conferencePaper

4 Scopus citations

Abstract

This paper presents a novel field-programmable gate array logic block architecture which incorporates support for digit-serial DSP architectures on a digit wide basis, without diminishing the support for random and control logic applications. To efficiently realize a digit-serial DSP design on FPGAs, one must create an FPGA architecture optimized for those types of systems. Key to the suitability of the FPGA for these applications is the fact that each of its basic blocks is capable of processing a digit-size of up to 4-bits. A novel digit-serial FPGA logic block architecture has been proposed to satisfy the requirement of rapid prototyping and efficient implementation of digit-serial DSP applications. Digit-serial DSP designs using the digit-serial FPGA are compared to those implemented on a Xilinx FPGA chip. The results show that the normalized area of digit-serial circuits on the DS-FPGA is only 33 to approximately 54% of the number required on the Xilinx FPGA.

Original languageEnglish (US)
Pages469-478
Number of pages10
StatePublished - Jan 1 1998
EventProceedings of the 1998 IEEE Workshop on Signal Processing Systems, SIPS - Cambridge, MA, USA
Duration: Oct 8 1998Oct 10 1998

Other

OtherProceedings of the 1998 IEEE Workshop on Signal Processing Systems, SIPS
CityCambridge, MA, USA
Period10/8/9810/10/98

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