A novel connection between digit-serial computing and skew-tolerant domino circuit design is developed and applied to the design of a 512-bit modular multiplier. In our design, a digit size of four bits is efficiently mapped onto a four-phase overlapping clocking scheme, so that four bits are processed during each full clock cycle. Our architecture is based on a modified interleaved multiplication algorithm and uses pre-computed complements of the modulus and a carry save adder scheme. We also present a technique for modeling time borrowing behavior in skew-tolerant domino using a VHDL behavioral description. This allows very large skew-tolerant domino circuits to be simulated efficiently in such a way that the essential time borrowing behavior is correctly represented. This simulation methodology is used to verify the correctness of our design and to determine its through-put.
|Original language||English (US)|
|Number of pages||4|
|Journal||ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings|
|State||Published - Jan 1 2001|