Digit-serial DSP library for optimized FPGA configuration

Hanho Lee, G. E. Sobelman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

This paper gives the digit-serial DSP libraries used to implement the digit-serial DSP architecture for field programmable gate arrays (FPGAs) and compares schematic-based FPGA design with design based on logic synthesis for digit-serial DSP libraries. It describes the design of digit-serial addition/subtraction, multiplication and delay elements and indicates also how digit-serial FIR filter can be implemented. The FPGA device utilization and critical path delay of digit-serial DSP libraries are calculated and described.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998
EditorsKenneth L. Pocek, Jeffrey M. Arnold
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-2
Number of pages2
ISBN (Electronic)0818689005, 9780818689000
DOIs
StatePublished - 1998
Event1998 IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998 - Napa Valley, United States
Duration: Apr 15 1998Apr 17 1998

Publication series

NameProceedings - IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998
Volume1998-April

Conference

Conference1998 IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998
CountryUnited States
CityNapa Valley
Period4/15/984/17/98

Bibliographical note

Funding Information:
This research was supported by Defense Advanced Research Project Agency under contract number DA/DABT63-96-C-0050. We would like to thank Keshab Parhi for valuable conversations.

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