This paper gives the digit-serial DSP libraries used to implement the digit-serial DSP architecture for field programmable gate arrays (FPGAs) and compares schematic-based FPGA design with design based on logic synthesis for digit-serial DSP libraries. It describes the design of digit-serial addition/subtraction, multiplication and delay elements and indicates also how digit-serial FIR filter can be implemented. The FPGA device utilization and critical path delay of digit-serial DSP libraries are calculated and described.
|Original language||English (US)|
|Title of host publication||Proceedings - IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998|
|Editors||Kenneth L. Pocek, Jeffrey M. Arnold|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|ISBN (Electronic)||0818689005, 9780818689000|
|State||Published - 1998|
|Event||1998 IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998 - Napa Valley, United States|
Duration: Apr 15 1998 → Apr 17 1998
|Name||Proceedings - IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998|
|Conference||1998 IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998|
|Period||4/15/98 → 4/17/98|
Bibliographical noteFunding Information:
This research was supported by Defense Advanced Research Project Agency under contract number DA/DABT63-96-C-0050. We would like to thank Keshab Parhi for valuable conversations.