Developments of SOI monolithic pixel detectors

Y. Arai; T. Miyoshi; Y. Unno; T. Tsuboyama; S. Terada; Y. Ikegami; T. Kohriki; K. Tauchi; Y. Ikemoto; R. Ichimiya; H. Ikeda; K. Hara; H. Miyake; M. Kochiyama; T. Sega; K. Hanagaki; M. Hirose; T. Hatsui; T. Kudo; T. Hirono; M. Yabashi; Y. Furukawa; G. Varner; M. Cooney; H. Hoedlmoser; J. Kennedy; H. Sahoo; M. Battaglia; P. Denes; C. Vu; D. Contarato; P. Giubilato; L. Glesener; R. Yarema; R. Lipton; G. Deptuch; M. Trimpl; M. Ohno; K. Fukuda; H. Komatsubara; J. Ida; M. Okihara; H. Hayashi; Y. Kawai; A. Ohtomo

doi:10.1016/j.nima.2010.02.190

Developments of SOI monolithic pixel detectors

Y. Arai, T. Miyoshi, Y. Unno, T. Tsuboyama, S. Terada, Y. Ikegami, T. Kohriki, K. Tauchi, Y. Ikemoto, R. Ichimiya, H. Ikeda, K. Hara, H. Miyake, M. Kochiyama, T. Sega, K. Hanagaki, M. Hirose, T. Hatsui, T. Kudo, T. HironoM. Yabashi, Y. Furukawa, G. Varner, M. Cooney, H. Hoedlmoser, J. Kennedy, H. Sahoo, M. Battaglia, P. Denes, C. Vu, D. Contarato, P. Giubilato, L. Glesener, R. Yarema, R. Lipton, G. Deptuch, M. Trimpl, M. Ohno, K. Fukuda, H. Komatsubara, J. Ida, M. Okihara, H. Hayashi, Y. Kawai, A. Ohtomo

Physics and Astronomy (Twin Cities)

Research output: Contribution to journal › Article › peer-review

48 Scopus citations

Abstract

A monolithic pixel detector with 0.2μm silicon-on-insulator (SOI) CMOS technology has been developed. It has both a thick high-resistivity sensor layer and thin LSI circuit layer on a single chip. Integration-type and counting-type pixel detectors are fabricated and tested with light and X-rays. The process is open to many researchers through Multi Project Wafer (MPW) runs operated by KEK. Further improvements of the fabrication technologies are also under investigation by using a buried p-well and 3D integration technologies.

Original language	English (US)
Pages (from-to)	186-188
Number of pages	3
Journal	Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
Volume	623
Issue number	1
DOIs	https://doi.org/10.1016/j.nima.2010.02.190
State	Published - Nov 1 2010

Bibliographical note

Funding Information:
The authors wish to thank F. Takasaki and J. Haba for their continuing support to this project. This work is supported by VLSI Design and Education Center (VDEC), The University of Tokyo with the collaboration of the Cadence Corporation and Mentor Graphics Corporation.

Keywords

Particle tracking
Pixel
SOI
X-ray imaging

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10.1016/j.nima.2010.02.190

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Arai, Y., Miyoshi, T., Unno, Y., Tsuboyama, T., Terada, S., Ikegami, Y., Kohriki, T., Tauchi, K., Ikemoto, Y., Ichimiya, R., Ikeda, H., Hara, K., Miyake, H., Kochiyama, M., Sega, T., Hanagaki, K., Hirose, M., Hatsui, T., Kudo, T., ... Ohtomo, A. (2010). Developments of SOI monolithic pixel detectors. Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 623(1), 186-188. https://doi.org/10.1016/j.nima.2010.02.190

Arai, Y, Miyoshi, T, Unno, Y, Tsuboyama, T, Terada, S, Ikegami, Y, Kohriki, T, Tauchi, K, Ikemoto, Y, Ichimiya, R, Ikeda, H, Hara, K, Miyake, H, Kochiyama, M, Sega, T, Hanagaki, K, Hirose, M, Hatsui, T, Kudo, T, Hirono, T, Yabashi, M, Furukawa, Y, Varner, G, Cooney, M, Hoedlmoser, H, Kennedy, J, Sahoo, H, Battaglia, M, Denes, P, Vu, C, Contarato, D, Giubilato, P, Glesener, L, Yarema, R, Lipton, R, Deptuch, G, Trimpl, M, Ohno, M, Fukuda, K, Komatsubara, H, Ida, J, Okihara, M, Hayashi, H, Kawai, Y & Ohtomo, A 2010, 'Developments of SOI monolithic pixel detectors', Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 623, no. 1, pp. 186-188. https://doi.org/10.1016/j.nima.2010.02.190

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abstract = "A monolithic pixel detector with 0.2μm silicon-on-insulator (SOI) CMOS technology has been developed. It has both a thick high-resistivity sensor layer and thin LSI circuit layer on a single chip. Integration-type and counting-type pixel detectors are fabricated and tested with light and X-rays. The process is open to many researchers through Multi Project Wafer (MPW) runs operated by KEK. Further improvements of the fabrication technologies are also under investigation by using a buried p-well and 3D integration technologies.",

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author = "Y. Arai and T. Miyoshi and Y. Unno and T. Tsuboyama and S. Terada and Y. Ikegami and T. Kohriki and K. Tauchi and Y. Ikemoto and R. Ichimiya and H. Ikeda and K. Hara and H. Miyake and M. Kochiyama and T. Sega and K. Hanagaki and M. Hirose and T. Hatsui and T. Kudo and T. Hirono and M. Yabashi and Y. Furukawa and G. Varner and M. Cooney and H. Hoedlmoser and J. Kennedy and H. Sahoo and M. Battaglia and P. Denes and C. Vu and D. Contarato and P. Giubilato and L. Glesener and R. Yarema and R. Lipton and G. Deptuch and M. Trimpl and M. Ohno and K. Fukuda and H. Komatsubara and J. Ida and M. Okihara and H. Hayashi and Y. Kawai and A. Ohtomo",

note = "Funding Information: The authors wish to thank F. Takasaki and J. Haba for their continuing support to this project. This work is supported by VLSI Design and Education Center (VDEC), The University of Tokyo with the collaboration of the Cadence Corporation and Mentor Graphics Corporation. ",

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doi = "10.1016/j.nima.2010.02.190",

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T1 - Developments of SOI monolithic pixel detectors

AU - Arai, Y.

AU - Miyoshi, T.

AU - Unno, Y.

AU - Tsuboyama, T.

AU - Terada, S.

AU - Ikegami, Y.

AU - Kohriki, T.

AU - Tauchi, K.

AU - Ikemoto, Y.

AU - Ichimiya, R.

AU - Ikeda, H.

AU - Hara, K.

AU - Miyake, H.

AU - Kochiyama, M.

AU - Sega, T.

AU - Hanagaki, K.

AU - Hirose, M.

AU - Hatsui, T.

AU - Kudo, T.

AU - Hirono, T.

AU - Yabashi, M.

AU - Furukawa, Y.

AU - Varner, G.

AU - Cooney, M.

AU - Hoedlmoser, H.

AU - Kennedy, J.

AU - Sahoo, H.

AU - Battaglia, M.

AU - Denes, P.

AU - Vu, C.

AU - Contarato, D.

AU - Giubilato, P.

AU - Glesener, L.

AU - Yarema, R.

AU - Lipton, R.

AU - Deptuch, G.

AU - Trimpl, M.

AU - Ohno, M.

AU - Fukuda, K.

AU - Komatsubara, H.

AU - Ida, J.

AU - Okihara, M.

AU - Hayashi, H.

AU - Kawai, Y.

AU - Ohtomo, A.

N1 - Funding Information: The authors wish to thank F. Takasaki and J. Haba for their continuing support to this project. This work is supported by VLSI Design and Education Center (VDEC), The University of Tokyo with the collaboration of the Cadence Corporation and Mentor Graphics Corporation.

PY - 2010/11/1

Y1 - 2010/11/1

N2 - A monolithic pixel detector with 0.2μm silicon-on-insulator (SOI) CMOS technology has been developed. It has both a thick high-resistivity sensor layer and thin LSI circuit layer on a single chip. Integration-type and counting-type pixel detectors are fabricated and tested with light and X-rays. The process is open to many researchers through Multi Project Wafer (MPW) runs operated by KEK. Further improvements of the fabrication technologies are also under investigation by using a buried p-well and 3D integration technologies.

AB - A monolithic pixel detector with 0.2μm silicon-on-insulator (SOI) CMOS technology has been developed. It has both a thick high-resistivity sensor layer and thin LSI circuit layer on a single chip. Integration-type and counting-type pixel detectors are fabricated and tested with light and X-rays. The process is open to many researchers through Multi Project Wafer (MPW) runs operated by KEK. Further improvements of the fabrication technologies are also under investigation by using a buried p-well and 3D integration technologies.

KW - Particle tracking

KW - Pixel

KW - SOI

KW - X-ray imaging

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JO - Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

JF - Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

IS - 1

ER -

Developments of SOI monolithic pixel detectors

Abstract

Bibliographical note

Keywords

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