Development of ultrabroadband (DC50 GHz) wafer-scale packaging method for low-profile bump flip-chip technology

Young Seek Cho, Rhonda Franklin-Drayton

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

A locally matched flip-chip (LMFC) interconnect that uses a capacitive compensation technique to minimize impedance mismatch in coplanar waveguide lines is described. With an optimum percentage change in capacitance of 55±5%, we observe return loss below 25 dB over 90% of a 50 GHz bandwidth. When compared to a conventional flip-chip method, the minimum performance improvement in return loss is 10 dB and the insertion loss is smooth up to 30 GHz. The LMFC interconnect consists of two micromachined features: 1) an air cavity underneath the chip and 2) local trenches in the transition region of the flip-chip interconnect interface. A comparison of different LMFC interconnect designs to the conventional flip-chip approach is made, and design rules to obtain local trench dimensions are discussed.

Original languageEnglish (US)
Article number5169972
Pages (from-to)788-796
Number of pages9
JournalIEEE Transactions on Advanced Packaging
Volume32
Issue number4
DOIs
StatePublished - Nov 1 2009

Keywords

  • Coplanar waveguides
  • Flip-chip devices
  • Gold alloys
  • Interconnected circuits
  • Interconnections
  • Micromachining
  • Tin alloys

Fingerprint

Dive into the research topics of 'Development of ultrabroadband (DC50 GHz) wafer-scale packaging method for low-profile bump flip-chip technology'. Together they form a unique fingerprint.

Cite this