Designing optimized pipelined global interconnects: Algorithms and methodology impact

Vidyasagar Nookala, Sachin S Sapatnekar

Research output: Contribution to journalConference articlepeer-review

16 Scopus citations

Abstract

As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of latencies along paths in the circuit, and this can cause the implemented circuit to have a different functionality than was intended by the designer. Although it is possible to use design techniques that maintain the functionality of the circuit, an additional concern is a reduction in the throughput. This may be overcome by careful choices at various stages of design that impact the across-chip wire latencies. This paper surveys the published work on wire-pipelining, describes its impact on circuit as well as system level throughput, and outlines some of the problems to be resolved in formulating a wirepipelining centric strategy for physical design.

Original languageEnglish (US)
Article number1464661
Pages (from-to)608-611
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - Dec 1 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: May 23 2005May 26 2005

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