Design techniques for pulsed static CMOS

Kavitha Seshadri, Adrianne Pontarelli, Gauri Joglekar, Gerald E Sobelman

Research output: Contribution to journalConference articlepeer-review


This paper gives new results in the design of Pulsed Static CMOS circuits. In particular, a new method of circuit duplication has been proposed which is particularly useful for the implementation of arithmetic functions. An array multiplier and a carry-select adder are used as representative design examples. Simulation results confirm that these Pulsed Static CMOS circuits operate correctly and have greater throughput than traditional static designs.

Original languageEnglish (US)
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - Sep 7 2004
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: May 23 2004May 26 2004


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