Design sensitivity of single event transients in scaled logic circuits

Keyphrases

• Logic Circuit 100%
• Design Sensitivity 100%
• Single-event Transient 100%
• Modern Technologies 33%
• Circuit Parameters 33%
• Vulnerability 16%
• Digital Circuits 16%
• Reliability Issues 16%
• Error Probability 16%
• Supply Voltage 16%
• Process Variation 16%
• Device Scaling 16%
• Technology Generation 16%
• Failure Probability 16%
• Probability Model 16%
• Single Event Upset 16%
• Parameter Tuning 16%
• Device Dimensions 16%
• Reliability Mechanism 16%
• Digital Logic 16%
• Transient Propagation 16%
• Process Reliability 16%
• Variability Mechanisms 16%
• Particle Strike 16%
• Critical Supplies 16%
• Proposed Methodology 16%

Engineering

• Logic Circuit 100%
• Circuit Parameter 100%
• Device Scaling 50%
• Nodes 50%
• Process Parameter 50%
• Generation Technology 50%
• Failure Probability 50%
• Single Event Upset 50%
• Supply Voltage 50%
• Process Variation 50%
• Digital Electronics 50%