Design of low-phase-noise CMOS ring oscillators

Liang Dai, Ramesh Harjani

Research output: Contribution to journalArticle

93 Scopus citations

Abstract

This paper presents a framework for modeling the phase noise in complementary metal-oxide-semiconductor (CMOS) ring oscillators. The analysis considers both linear and nonlinear operations, and it includes both device noise and digital switching noise coupled through the power supply and substrate. In this paper, we show that fast rail-to-rail switching is required in order to achieve low phase noise. Further, flicker noise from the bias circuit can potentially dominate the phase noise at low offset frequencies. We define the effective Q factor for ring oscillators with large and nonlinear voltage swings and predict its increase for CMOS processes with smaller feature sizes. Our phase-noise analysis is validated via simulation and measurement results for ring oscillators fabricated in a number of CMOS processes.

Original languageEnglish (US)
Pages (from-to)328-338
Number of pages11
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume49
Issue number5
DOIs
StatePublished - May 1 2002

Keywords

  • Complementary metal-oxide-semiconductor (CMOS) ring oscillator
  • Phase noise
  • Timing jitter
  • Voltage-controlled oscillator (VCO)

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