Design of low-error fixed-width modified booth multiplier

Kyung Ju Cho, Kwang Chul Lee, Jin Gyun Chung, Keshab K Parhi

Research output: Contribution to journalArticlepeer-review

134 Scopus citations


This paper presents an error compensation method for a modified Booth fixed-width multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50% by the proposed error compensation method compared with the existing method with approximately the same hardware overhead in the bias generation circuit. It is also shown that the proposed method leads to up to 35% reduction in area and power consumption of a multiplier compared with the ideal multiplier.

Original languageEnglish (US)
Pages (from-to)522-531
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number5
StatePublished - May 1 2004


  • Approximate carry
  • Fixed-width multiplier
  • Modified booth multiplier
  • Quantization

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