Design of low error CSD fixed-width multiplier

This paper presents an error compensation method for a canonic signed digit (CSD) fixed-width multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, the truncated bits are divided into two groups (major group and minor group) depending upon their effects on the quantization error. The desired error compensation bias is first expressed in terms of the truncated bits in the major group. Then the effects of the other truncated bits in the minor group are taken care of by a probabilistic estimation. The design of error compensation bias circuit requires only a few logic gates in most cases. By simulations, it is shown that significant reduction in the truncation error can be achieved by the proposed error compensation method.