DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as cache-only memory architecture (COMA). Unlike previous COMA proposals for large-scale multiprocessing, DICE utilizes COMA to effectively decrease the speed gap between modem high-performance microprocessors and the bus. DICE tries to optimize COMA for a shared-bus medium, in particular to reduce detrimental effects of the cache coherence and the 'last memory block' problem on replacement. In this paper, we present a global bus design of DICE based on the IEEE futurebus + backplane bus and the Texas Instruments chip-set. Our design demonstrates that necessary bus transactions for DICE can be done efficiently with existing standard bus signals. Considering the benefits of COMA and the moderate design complexity it adds to the conventional shared-bus multiprocessor design, a bus-based COMA multiprocessor, such as DICE, can become a viable candidate for future shared-bus multiprocessor designs.
Bibliographical noteFunding Information:
The DICE project was supported by funding from Samsung Electronics, Seoul, Korea. Manu Agarwal, Sujat Jamil and Jinseok Kong contributed to the project on which this work is based. An earlier version of the paper was presented in Ref.  .
Copyright 2017 Elsevier B.V., All rights reserved.
- Cache-only memory architecture
- Coherence protocol
- Memory replacement
- Shared bus