Design Methodology of a 1.2-μm Double-Level-Metal CMOS Technology

Nancy E. Preckshot, Stephen A. Campbell, Walter W. Heikkila, Dimitri Dokos, Robin H. Passow, Wesley N. Grant, Dale Schultz, John P. Victorey

Research output: Contribution to journalArticle


An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-μm gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.

Original languageEnglish (US)
Pages (from-to)215-225
Number of pages11
JournalIEEE Transactions on Electron Devices
Issue number2
StatePublished - Feb 1984

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    Preckshot, N. E., Campbell, S. A., Heikkila, W. W., Dokos, D., Passow, R. H., Grant, W. N., Schultz, D., & Victorey, J. P. (1984). Design Methodology of a 1.2-μm Double-Level-Metal CMOS Technology. IEEE Transactions on Electron Devices, 31(2), 215-225.