Design Limits of In-Memory Computing: Beyond the Crossbar

Gokul Krishnan; Jubin Hazra; Maximilian Liehr; Xiaocong Du; Karsten Beckmann; Rajiv V. Joshi; Nathaniel C. Cady; Yu Cao

doi:10.1109/EDTM50988.2021.9421057

Design Limits of In-Memory Computing: Beyond the Crossbar

Gokul Krishnan, Jubin Hazra, Maximilian Liehr, Xiaocong Du, Karsten Beckmann, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

Resistive random-access memory (RRAM)-based in-memory computing (IMC) architecture offers an energy-efficient solution for DNN acceleration. Yet, its performance is limited by device non-idealities, circuit precision, on-chip interconnection, and algorithm properties. Based on statistical data from a fully-integrated 65nm CMOS/RRAM test chip and a cross-layer simulation framework, we show that the IMC system's real bottleneck is not the RRAM device but the analog-to-digital converter (ADC) precision and the stability of DNN models. The results are summarized into a roofline model and demonstrated on CIFAR-10, SVHN, CIFAR-100, and ImageNet, helping understand RRAM-based IMC architectures' design limits.

Original language	English (US)
Title of host publication	2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728181769
DOIs	https://doi.org/10.1109/EDTM50988.2021.9421057
State	Published - Apr 8 2021
Externally published	Yes
Event	5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021 - Chengdu, China Duration: Apr 8 2021 → Apr 11 2021

Publication series

Name	2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021

Conference

Conference	5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
Country/Territory	China
City	Chengdu
Period	4/8/21 → 4/11/21

Bibliographical note

Funding Information:
This work was supported in part by the Semiconductor Research Corporation (SRC) and DARPA, the National Science Foundation (NSF) under CCF-1715443, and the Air Force Research Laboratory award #FA8750-19-1-0014.

Publisher Copyright:
© 2021 IEEE.

Publisher link

10.1109/EDTM50988.2021.9421057

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Cite this

Krishnan, G., Hazra, J., Liehr, M., Du, X., Beckmann, K., Joshi, R. V., Cady, N. C., & Cao, Y. (2021). Design Limits of In-Memory Computing: Beyond the Crossbar. In 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021 Article 9421057 (2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDTM50988.2021.9421057

Design Limits of In-Memory Computing: Beyond the Crossbar. / Krishnan, Gokul; Hazra, Jubin; Liehr, Maximilian et al.
2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021. Institute of Electrical and Electronics Engineers Inc., 2021. 9421057 (2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Krishnan, G, Hazra, J, Liehr, M, Du, X, Beckmann, K, Joshi, RV, Cady, NC & Cao, Y 2021, Design Limits of In-Memory Computing: Beyond the Crossbar. in 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021., 9421057, 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021, Institute of Electrical and Electronics Engineers Inc., 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021, Chengdu, China, 4/8/21. https://doi.org/10.1109/EDTM50988.2021.9421057

Krishnan G, Hazra J, Liehr M, Du X, Beckmann K, Joshi RV et al. Design Limits of In-Memory Computing: Beyond the Crossbar. In 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021. Institute of Electrical and Electronics Engineers Inc. 2021. 9421057. (2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021). doi: 10.1109/EDTM50988.2021.9421057

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title = "Design Limits of In-Memory Computing: Beyond the Crossbar",

abstract = "Resistive random-access memory (RRAM)-based in-memory computing (IMC) architecture offers an energy-efficient solution for DNN acceleration. Yet, its performance is limited by device non-idealities, circuit precision, on-chip interconnection, and algorithm properties. Based on statistical data from a fully-integrated 65nm CMOS/RRAM test chip and a cross-layer simulation framework, we show that the IMC system's real bottleneck is not the RRAM device but the analog-to-digital converter (ADC) precision and the stability of DNN models. The results are summarized into a roofline model and demonstrated on CIFAR-10, SVHN, CIFAR-100, and ImageNet, helping understand RRAM-based IMC architectures' design limits.",

author = "Gokul Krishnan and Jubin Hazra and Maximilian Liehr and Xiaocong Du and Karsten Beckmann and Joshi, {Rajiv V.} and Cady, {Nathaniel C.} and Yu Cao",

note = "Funding Information: This work was supported in part by the Semiconductor Research Corporation (SRC) and DARPA, the National Science Foundation (NSF) under CCF-1715443, and the Air Force Research Laboratory award #FA8750-19-1-0014. Publisher Copyright: {\textcopyright} 2021 IEEE.; 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021 ; Conference date: 08-04-2021 Through 11-04-2021",

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AU - Beckmann, Karsten

AU - Joshi, Rajiv V.

AU - Cady, Nathaniel C.

AU - Cao, Yu

N1 - Funding Information: This work was supported in part by the Semiconductor Research Corporation (SRC) and DARPA, the National Science Foundation (NSF) under CCF-1715443, and the Air Force Research Laboratory award #FA8750-19-1-0014. Publisher Copyright: © 2021 IEEE.

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N2 - Resistive random-access memory (RRAM)-based in-memory computing (IMC) architecture offers an energy-efficient solution for DNN acceleration. Yet, its performance is limited by device non-idealities, circuit precision, on-chip interconnection, and algorithm properties. Based on statistical data from a fully-integrated 65nm CMOS/RRAM test chip and a cross-layer simulation framework, we show that the IMC system's real bottleneck is not the RRAM device but the analog-to-digital converter (ADC) precision and the stability of DNN models. The results are summarized into a roofline model and demonstrated on CIFAR-10, SVHN, CIFAR-100, and ImageNet, helping understand RRAM-based IMC architectures' design limits.

AB - Resistive random-access memory (RRAM)-based in-memory computing (IMC) architecture offers an energy-efficient solution for DNN acceleration. Yet, its performance is limited by device non-idealities, circuit precision, on-chip interconnection, and algorithm properties. Based on statistical data from a fully-integrated 65nm CMOS/RRAM test chip and a cross-layer simulation framework, we show that the IMC system's real bottleneck is not the RRAM device but the analog-to-digital converter (ADC) precision and the stability of DNN models. The results are summarized into a roofline model and demonstrated on CIFAR-10, SVHN, CIFAR-100, and ImageNet, helping understand RRAM-based IMC architectures' design limits.

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Design Limits of In-Memory Computing: Beyond the Crossbar

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