Design in hot-carrier reliability for high performance logic applications

Peng Fang, Jiang Tao, Jone F. Chen, Chenming Hu

Research output: Contribution to journalConference article

30 Citations (Scopus)

Abstract

Static (DC) and dynamic (AC) hot carrier degradation mechanisms were reviewed. Circuit performance degradation has been correlated to individual NMOS or PMOS device under DC stress. AC degradation model calibration and evaluation guidelines were also reviewed to ensure the use of hot-carrier reliability simulation tools in circuit level. As an example, thousand-hour inverter ring oscillator speed degradation data with different fanout, stress voltages, channel length, and processes are compared with that obtained from reliability simulation. The results show that reliability simulation is a powerful tool for logic circuit design optimization. It can predict the long-term circuit hot-carrier degradation accurately. The reliability of inverter, NAND, and NOR structures are also simulated and compared.

Original languageEnglish (US)
Pages (from-to)525-531
Number of pages7
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - Jan 1 1998
Externally publishedYes
EventProceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: May 11 1998May 14 1998

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Hot carriers
Degradation
Networks (circuits)
Logic design
Calibration
Electric potential

Cite this

Design in hot-carrier reliability for high performance logic applications. / Fang, Peng; Tao, Jiang; Chen, Jone F.; Hu, Chenming.

In: Proceedings of the Custom Integrated Circuits Conference, 01.01.1998, p. 525-531.

Research output: Contribution to journalConference article

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