The IMS A110 provides a solution to many real-time image- and signal-processing problems by supporting techniques such as 1-D/2-D convolution/correlation, statistical/histogram data collection and nonlinear data transformation. It is a cascadable, software configurable single-chip digital signal-processing device that operates at 20 MHz with a data throughput of 420 MOPS (million operations per second), and consists of three programmable length shift registers, a configurable 21-stage multiply-accumulate array (MAC), a postprocessing unit (PPU) and a microprocessor interface. The chip is fabricated in a single-level-metal 1.2-μm polysilicide CMOS process and contains around 375K transistors on a 9.6-mm × 8.1-mm die, which translates to a site density of 4.1 transistors/mil2 (excluding the pad ring). The authors present an overview of the A110 architecture and highlight the key design techniques used to implement the multiply accumulate array.
|Original language||English (US)|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - May 1 1989|
|Event||Proceedings of the IEEE 1989 Custom Integrated Circuits Conference - San Diego, CA, SA|
Duration: May 15 1989 → May 18 1989