Design and implementation of LDPC codes for DVB-S2

Manoj K. Yadav; Keshab K Parhi

Design and implementation of LDPC codes for DVB-S2

Manoj K. Yadav, Keshab K Parhi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

In this paper, we present the design and FPGA implementation of 11 LDPC codes with code rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10 for normal frame length of 64800 bits as used in DVB-S2. Out of these 11 codes, 7 are regular and 4 are irregular. All of them have been synthesized into Xilinx Virtex-II XC2V8000 FPGA.

Original language	English (US)
Title of host publication	Conference Record of The Thirty-Ninth Asilomar Conference on Signals, Systems and Computers
Pages	723-728
Number of pages	6
State	Published - Dec 1 2005
Event	39th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, United States Duration: Oct 28 2005 → Nov 1 2005

Publication series

Name	Conference Record - Asilomar Conference on Signals, Systems and Computers
Volume	2005
ISSN (Print)	1058-6393

Other

Other	39th Asilomar Conference on Signals, Systems and Computers
Country/Territory	United States
City	Pacific Grove, CA
Period	10/28/05 → 11/1/05

Find It

Find It at U of M Libraries

Cite this

Design and implementation of LDPC codes for DVB-S2. / Yadav, Manoj K.; Parhi, Keshab K.

Conference Record of The Thirty-Ninth Asilomar Conference on Signals, Systems and Computers. 2005. p. 723-728 1599847 (Conference Record - Asilomar Conference on Signals, Systems and Computers; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yadav, MK & Parhi, KK 2005, Design and implementation of LDPC codes for DVB-S2. in Conference Record of The Thirty-Ninth Asilomar Conference on Signals, Systems and Computers., 1599847, Conference Record - Asilomar Conference on Signals, Systems and Computers, vol. 2005, pp. 723-728, 39th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, United States, 10/28/05.

@inproceedings{1de8302774cf4a369c76a4e72d6315dc,

title = "Design and implementation of LDPC codes for DVB-S2",

abstract = "In this paper, we present the design and FPGA implementation of 11 LDPC codes with code rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10 for normal frame length of 64800 bits as used in DVB-S2. Out of these 11 codes, 7 are regular and 4 are irregular. All of them have been synthesized into Xilinx Virtex-II XC2V8000 FPGA.",

author = "Yadav, {Manoj K.} and Parhi, {Keshab K}",

year = "2005",

month = dec,

day = "1",

language = "English (US)",

isbn = "1424401313",

series = "Conference Record - Asilomar Conference on Signals, Systems and Computers",

pages = "723--728",

booktitle = "Conference Record of The Thirty-Ninth Asilomar Conference on Signals, Systems and Computers",

note = "39th Asilomar Conference on Signals, Systems and Computers ; Conference date: 28-10-2005 Through 01-11-2005",

}

TY - GEN

T1 - Design and implementation of LDPC codes for DVB-S2

AU - Yadav, Manoj K.

AU - Parhi, Keshab K

PY - 2005/12/1

Y1 - 2005/12/1

N2 - In this paper, we present the design and FPGA implementation of 11 LDPC codes with code rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10 for normal frame length of 64800 bits as used in DVB-S2. Out of these 11 codes, 7 are regular and 4 are irregular. All of them have been synthesized into Xilinx Virtex-II XC2V8000 FPGA.

AB - In this paper, we present the design and FPGA implementation of 11 LDPC codes with code rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10 for normal frame length of 64800 bits as used in DVB-S2. Out of these 11 codes, 7 are regular and 4 are irregular. All of them have been synthesized into Xilinx Virtex-II XC2V8000 FPGA.

UR - http://www.scopus.com/inward/record.url?scp=33847645065&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33847645065&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:33847645065

SN - 1424401313

SN - 9781424401314

T3 - Conference Record - Asilomar Conference on Signals, Systems and Computers

SP - 723

EP - 728

BT - Conference Record of The Thirty-Ninth Asilomar Conference on Signals, Systems and Computers

T2 - 39th Asilomar Conference on Signals, Systems and Computers

Y2 - 28 October 2005 through 1 November 2005

ER -

Design and implementation of LDPC codes for DVB-S2

Abstract

Publication series

Other

Find It

Other files and links

Fingerprint

Cite this