Derivation of signal flow directions and synchronizers for switch-level timing analysis

Juho Kim, Joo sang Lee, David H.C. Du

Research output: Contribution to journalConference articlepeer-review

Abstract

Signal flow directions and synchronizers in switch-level circuits are useful information in both simulation and timing analysis. Since signal flow of a transistor may get changed at different clock phases, our new approach of assigning signal flow directions incorporates with synchronizers. Our algorithm takes a global approach by assigning signal flow directions and synchronizers of transistors simultaneously from the graphical representation of a circuit. In our approach, functionality of a circuit is considered to determine signal flow directions, synchronizers, and feasible transitions. Our experimental results show that our algorithm is effective in both static and dynamic CMOS circuits with reasonable time and space.

Original languageEnglish (US)
Pages (from-to)548-551
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
StatePublished - Jan 1 1996
EventProceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA
Duration: May 12 1996May 15 1996

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