Delay-line-based analog-to-digital converters

Guansheng Li; Yahya M. Tousi; Arjang Hassibi; Ehsan Afshari

doi:10.1109/TCSII.2009.2020947

Delay-line-based analog-to-digital converters

Guansheng Li, Yahya M. Tousi, Arjang Hassibi, Ehsan Afshari

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

113 Scopus citations

Abstract

We will introduce a design of analog-to-digital converters (ADCs) based on digital delay lines. Instead of voltage comparators, they convert the input voltage into a digital code by delay lines and are mainly built on digital blocks. This makes it compatible with process scaling. Two structures are proposed, and tradeoffs in the design are discussed. The effects of jitter and mismatch are also studied. We will present two 4-bit, 1-GS/s prototypes in 0.13-μ and 65-nm CMOS processes, which show a small area (0.015 mm²) and small power consumption (< 2.4 mW).

Original language	English (US)
Pages (from-to)	464-468
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	56
Issue number	6
DOIs	https://doi.org/10.1109/TCSII.2009.2020947
State	Published - 2009

Bibliographical note

Funding Information:
Manuscript received October 27, 2008; revised February 7, 2009. Current version published June 17, 2009. The work of E. Afshari was supported by the Defense Advanced Research Projects Agency under the Young Faculty Award Program. This paper was recommended by Associate Editor K.-P. Pun.

Keywords

Analog-to-digital converter (ADC)
Delay line
Scaling

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10.1109/TCSII.2009.2020947

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@article{fee84a59eaea43d5b268d4bfc9d4ef15,

title = "Delay-line-based analog-to-digital converters",

abstract = "We will introduce a design of analog-to-digital converters (ADCs) based on digital delay lines. Instead of voltage comparators, they convert the input voltage into a digital code by delay lines and are mainly built on digital blocks. This makes it compatible with process scaling. Two structures are proposed, and tradeoffs in the design are discussed. The effects of jitter and mismatch are also studied. We will present two 4-bit, 1-GS/s prototypes in 0.13-μ and 65-nm CMOS processes, which show a small area (0.015 mm2) and small power consumption (< 2.4 mW).",

keywords = "Analog-to-digital converter (ADC), Delay line, Scaling",

author = "Guansheng Li and Tousi, {Yahya M.} and Arjang Hassibi and Ehsan Afshari",

note = "Funding Information: Manuscript received October 27, 2008; revised February 7, 2009. Current version published June 17, 2009. The work of E. Afshari was supported by the Defense Advanced Research Projects Agency under the Young Faculty Award Program. This paper was recommended by Associate Editor K.-P. Pun.",

year = "2009",

doi = "10.1109/TCSII.2009.2020947",

language = "English (US)",

volume = "56",

pages = "464--468",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - Delay-line-based analog-to-digital converters

AU - Li, Guansheng

AU - Tousi, Yahya M.

AU - Hassibi, Arjang

AU - Afshari, Ehsan

N1 - Funding Information: Manuscript received October 27, 2008; revised February 7, 2009. Current version published June 17, 2009. The work of E. Afshari was supported by the Defense Advanced Research Projects Agency under the Young Faculty Award Program. This paper was recommended by Associate Editor K.-P. Pun.

PY - 2009

Y1 - 2009

N2 - We will introduce a design of analog-to-digital converters (ADCs) based on digital delay lines. Instead of voltage comparators, they convert the input voltage into a digital code by delay lines and are mainly built on digital blocks. This makes it compatible with process scaling. Two structures are proposed, and tradeoffs in the design are discussed. The effects of jitter and mismatch are also studied. We will present two 4-bit, 1-GS/s prototypes in 0.13-μ and 65-nm CMOS processes, which show a small area (0.015 mm2) and small power consumption (< 2.4 mW).

AB - We will introduce a design of analog-to-digital converters (ADCs) based on digital delay lines. Instead of voltage comparators, they convert the input voltage into a digital code by delay lines and are mainly built on digital blocks. This makes it compatible with process scaling. Two structures are proposed, and tradeoffs in the design are discussed. The effects of jitter and mismatch are also studied. We will present two 4-bit, 1-GS/s prototypes in 0.13-μ and 65-nm CMOS processes, which show a small area (0.015 mm2) and small power consumption (< 2.4 mW).

KW - Analog-to-digital converter (ADC)

KW - Delay line

KW - Scaling

UR - http://www.scopus.com/inward/record.url?scp=67650165347&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=67650165347&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2009.2020947

DO - 10.1109/TCSII.2009.2020947

M3 - Article

AN - SCOPUS:67650165347

SN - 1549-7747

VL - 56

SP - 464

EP - 468

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 6

ER -

Delay-line-based analog-to-digital converters

Abstract

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Keywords

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