Delay and area optimization for discrete gate sizes under double-sided timing constraints

Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

A three-step algorithm is presented for discrete gate sizing problem of delay/area optimization under double-sided timing constraints. The problem is first formulated as a linear program. The solution to the linear program is the mapped onto a permissible set. Using this permissible set, the gate sizes are adjusted to satisfy the delay lower and upper bounds simultaneously.

Original languageEnglish (US)
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherPubl by IEEE
ISBN (Print)0780308263
StatePublished - Jan 1 1993
EventProceedings of the IEEE 1993 Custom Integrated Circuits Conference - San Diego, CA, USA
Duration: May 9 1993May 12 1993

Other

OtherProceedings of the IEEE 1993 Custom Integrated Circuits Conference
CitySan Diego, CA, USA
Period5/9/935/12/93

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