Defect-tolerant FPGA architecture exploration

Pongstorn Maidee; Kia Bazargan

doi:10.1109/FPL.2006.311253

Defect-tolerant FPGA architecture exploration

Pongstorn Maidee
, Kia Bazargan

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

According to the ITRS predictions, controlling manufacturing yield is going to be a challenging task in future technologies. The effective yield of future FPGA architectures considering configurable logic blocks, switch boxes, connection boxes and routing segments is estimated in this paper. The results show that some degree of redundancy for logic blocks, routing and switch boxes is necessary. However, no more than one spare logic block per cluster, and at most one spare wire is required to obtain a satisfactory effective yield. The results also indicate that it is beneficial to increase logic cluster size of future FPGA architectures for better yield.

Original language	English (US)
Title of host publication	Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
Pages	467-472
Number of pages	6
DOIs	https://doi.org/10.1109/FPL.2006.311253
State	Published - Dec 1 2006
Event	2006 International Conference on Field Programmable Logic and Applications, FPL - Madrid, Spain Duration: Aug 28 2006 → Aug 30 2006

Publication series

Name	Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Conference

Conference	2006 International Conference on Field Programmable Logic and Applications, FPL
Country/Territory	Spain
City	Madrid
Period	8/28/06 → 8/30/06

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

Publisher link

10.1109/FPL.2006.311253

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Defect-tolerant FPGA architecture exploration. / Maidee, Pongstorn; Bazargan, Kia.
Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. 2006. p. 467-472 4101015 (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Maidee, P & Bazargan, K 2006, Defect-tolerant FPGA architecture exploration. in Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL., 4101015, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL, pp. 467-472, 2006 International Conference on Field Programmable Logic and Applications, FPL, Madrid, Spain, 8/28/06. https://doi.org/10.1109/FPL.2006.311253

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ER -

Defect-tolerant FPGA architecture exploration

Abstract

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Conference

UN SDGs

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