Deep Neural Network Training Accelerator Designs in ASIC and FPGA

Shreyas K. Venkataramanaiah; Shihui Yin; Yu Cao; Jae Sun Seo

doi:10.1109/ISOCC50952.2020.9333063

Deep Neural Network Training Accelerator Designs in ASIC and FPGA

Shreyas K. Venkataramanaiah, Shihui Yin, Yu Cao, Jae Sun Seo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

19 Scopus citations

Abstract

In this invited paper, we present deep neural network (DNN) training accelerator designs in both ASIC and FPGA. The accelerators implements stochastic gradient descent based training algorithm in 16-bit fixed-point precision. A new cyclic weight storage and access scheme enables using the same off-The-shelf SRAMs for non-Transpose and transpose operations during feed-forward and feed-backward phases, respectively, of the DNN training process. Including the cyclic weight scheme, the overall DNN training processor is implemented in both 65nm CMOS ASIC and Intel Stratix-10 FPGA hardware. We collectively report the ASIC and FPGA training accelerator results.

Original language	English (US)
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	21-22
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9333063
State	Published - Oct 21 2020
Externally published	Yes
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: Oct 21 2020 → Oct 24 2020

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	10/21/20 → 10/24/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Keywords

convolutional neural networks
energy efficiency
hardware accelerator
on-device training

Publisher link

10.1109/ISOCC50952.2020.9333063

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Venkataramanaiah, S. K., Yin, S., Cao, Y., & Seo, J. S. (2020). Deep Neural Network Training Accelerator Designs in ASIC and FPGA. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 21-22). Article 9333063 (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9333063

Deep Neural Network Training Accelerator Designs in ASIC and FPGA. / Venkataramanaiah, Shreyas K.; Yin, Shihui; Cao, Yu et al.
Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 21-22 9333063 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Venkataramanaiah, SK, Yin, S, Cao, Y & Seo, JS 2020, Deep Neural Network Training Accelerator Designs in ASIC and FPGA. in Proceedings - International SoC Design Conference, ISOCC 2020., 9333063, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 21-22, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 10/21/20. https://doi.org/10.1109/ISOCC50952.2020.9333063

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abstract = "In this invited paper, we present deep neural network (DNN) training accelerator designs in both ASIC and FPGA. The accelerators implements stochastic gradient descent based training algorithm in 16-bit fixed-point precision. A new cyclic weight storage and access scheme enables using the same off-The-shelf SRAMs for non-Transpose and transpose operations during feed-forward and feed-backward phases, respectively, of the DNN training process. Including the cyclic weight scheme, the overall DNN training processor is implemented in both 65nm CMOS ASIC and Intel Stratix-10 FPGA hardware. We collectively report the ASIC and FPGA training accelerator results.",

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AB - In this invited paper, we present deep neural network (DNN) training accelerator designs in both ASIC and FPGA. The accelerators implements stochastic gradient descent based training algorithm in 16-bit fixed-point precision. A new cyclic weight storage and access scheme enables using the same off-The-shelf SRAMs for non-Transpose and transpose operations during feed-forward and feed-backward phases, respectively, of the DNN training process. Including the cyclic weight scheme, the overall DNN training processor is implemented in both 65nm CMOS ASIC and Intel Stratix-10 FPGA hardware. We collectively report the ASIC and FPGA training accelerator results.

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Deep Neural Network Training Accelerator Designs in ASIC and FPGA

Abstract

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Bibliographical note

Keywords

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