Methodologies are addressed for high-level synthesis of dedicated digital signal processing (DSP) architectures using the Minnesota architecture synthesis (MARS) design system. The MARS system is capable of exploring a wide design space because the authors' synthesis algorithms can accommodate multiple implementation styles. Algorithms are given for concurrent scheduling and resource allocation for systematic synthesis of DSP architectures. The algorithms exploit inter-iteration and intra-iteration precedence constraints, and produces as good or better results than those published. Synthesis is accommodated with multiple implementation styles to reduce overall hardware costs; systematic synthesis of such architectures has not been explored so far. To improve the quality of the final schedule, the algorithm utilizes implicit retiming and pipelining of the data flow graph.