Abstract
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on the predicted outcome. In this paper, we address several implementation issues for value prediction which are important on wide-issue superscalar architectures, and present a value prediction scheme based on the trace processor [18]. The scheme decouples the value prediction from the instruction fetch stage and use a hybrid predictor with dynamic classification. We use execution-driven simulation to study the performance of such a scheme using SPECint95 benchmarks.
Original language | English (US) |
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Title of host publication | IEEE High-Performance Computer Architecture Symposium Proceedings |
Pages | 231-240 |
Number of pages | 10 |
State | Published - 2000 |
Event | The 6th International Symposium on High-Performance Computer Architecture (HPCA-6) - Toulouse, France Duration: Jan 8 2000 → Jan 12 2000 |
Other
Other | The 6th International Symposium on High-Performance Computer Architecture (HPCA-6) |
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City | Toulouse, France |
Period | 1/8/00 → 1/12/00 |