Decoupled value prediction on trace processors

Sang Jeong Lee, Yuan Wang, Pen Chung Yew

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations


Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on the predicted outcome. In this paper, we address several implementation issues for value prediction which are important on wide-issue superscalar architectures, and present a value prediction scheme based on the trace processor [18]. The scheme decouples the value prediction from the instruction fetch stage and use a hybrid predictor with dynamic classification. We use execution-driven simulation to study the performance of such a scheme using SPECint95 benchmarks.

Original languageEnglish (US)
Title of host publicationIEEE High-Performance Computer Architecture Symposium Proceedings
Number of pages10
StatePublished - 2000
EventThe 6th International Symposium on High-Performance Computer Architecture (HPCA-6) - Toulouse, France
Duration: Jan 8 2000Jan 12 2000


OtherThe 6th International Symposium on High-Performance Computer Architecture (HPCA-6)
CityToulouse, France

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