@inproceedings{b564bfb7c3ac4774b9734e809a2ec329,
title = "DCOS: Cache embedded switch architecture for distributed shared memory multiprocessor SoCs",
abstract = "Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection networks plays a critical role in shared memory MPSoC designs. In this paper, we propose a directory-cache embedded switch architecture with distributed shared cache and distributed shared memory. It is able to reduce the number of home node cache accesses, which results in a reduction in the inter-cache transfer time and the total execution time. Simulation results verify that the proposed methodology can improve performance substantially over a design in which directory caches are not embedded in the switches.",
author = "Daewook Kim and Manho Kim and Sobelman, {Gerald E.}",
year = "2006",
language = "English (US)",
isbn = "0780393902",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
pages = "979--982",
booktitle = "ISCAS 2006",
note = "ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems ; Conference date: 21-05-2006 Through 24-05-2006",
}