@inproceedings{2e112d8989964fc585685448dd27085f,
title = "DAG based library-free technology mapping",
abstract = "This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through the longest path, considering that each cell network has to obey to a maximum admitted chain. The number of series transistors is computed in a Boolean way, reducing the structural bias. The mapping algorithm is performed on a Directed Acyclic Graph (DAG) description of the circuit. Preliminary results for delay were obtained through SPICE simulations. When compared to the SIS technology mapping, the proposed method shows significant delay reductions, considering circuits mapped with different libraries.",
keywords = "Library free synthesis, Logic synthesis, Switching theory, Technology mapping, Virtual libraries",
author = "Marques, {F. S.} and Rosa, {L. S.} and Ribas, {R. P.} and Sapatnekar, {S. S.} and Reis, {A. I.}",
note = "Copyright: Copyright 2008 Elsevier B.V., All rights reserved.; 17th Great Lakes Symposium on VLSI, GLSVLSI'07 ; Conference date: 11-03-2007 Through 13-03-2007",
year = "2007",
doi = "10.1145/1228784.1228857",
language = "English (US)",
isbn = "159593605X",
series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",
pages = "293--298",
booktitle = "GLSVLSI'07",
}