DAG based library-free technology mapping

F. S. Marques, L. S. Rosa, R. P. Ribas, S. S. Sapatnekar, A. I. Reis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Scopus citations


This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through the longest path, considering that each cell network has to obey to a maximum admitted chain. The number of series transistors is computed in a Boolean way, reducing the structural bias. The mapping algorithm is performed on a Directed Acyclic Graph (DAG) description of the circuit. Preliminary results for delay were obtained through SPICE simulations. When compared to the SIS technology mapping, the proposed method shows significant delay reductions, considering circuits mapped with different libraries.

Original languageEnglish (US)
Title of host publicationGLSVLSI'07
Subtitle of host publicationProceedings of the 2007 ACM Great Lakes Symposium on VLSI
Number of pages6
StatePublished - 2007
Event17th Great Lakes Symposium on VLSI, GLSVLSI'07 - Stresa-Lago Maggiore, Italy
Duration: Mar 11 2007Mar 13 2007

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI


Other17th Great Lakes Symposium on VLSI, GLSVLSI'07
CityStresa-Lago Maggiore


  • Library free synthesis
  • Logic synthesis
  • Switching theory
  • Technology mapping
  • Virtual libraries


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