TY - GEN
T1 - Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec
AU - Gao, Lijun
AU - Parhi, Keshnb K.
PY - 2001
Y1 - 2001
N2 - The issue of VLSI design of low latency/low power finite field multipliers is addressed and methods from logic structure, circuit design and physical mapping aspects are presented. With proposed architecture and physical mapping, an irregular balanced-tree parallel multiplier con be implemented as easy as a regular multiplier. The custom VLSI implementations of these multipliers over GF(2/sup m/) show that the irregular multiplier has 53% smaller delay and 58% less power consumption than a regular multiplier.
AB - The issue of VLSI design of low latency/low power finite field multipliers is addressed and methods from logic structure, circuit design and physical mapping aspects are presented. With proposed architecture and physical mapping, an irregular balanced-tree parallel multiplier con be implemented as easy as a regular multiplier. The custom VLSI implementations of these multipliers over GF(2/sup m/) show that the irregular multiplier has 53% smaller delay and 58% less power consumption than a regular multiplier.
UR - https://www.scopus.com/pages/publications/84888017782
UR - https://www.scopus.com/pages/publications/84888017782#tab=citedBy
U2 - 10.1109/ISCAS.2001.922302
DO - 10.1109/ISCAS.2001.922302
M3 - Conference contribution
AN - SCOPUS:84888017782
SN - 0780366859
SN - 9780780366855
T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
SP - 574
EP - 577
BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
T2 - 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Y2 - 6 May 2001 through 9 May 2001
ER -