Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec

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Abstract

The issue of VLSI design of low latency/low power finite field multipliers is addressed and methods from logic structure, circuit design and physical mapping aspects are presented. With proposed architecture and physical mapping, an irregular balanced-tree parallel multiplier can be implemented as easy as a regular multiplier. The custom VLSI implementations of these multipliers over GF(28) show that the irregular multiplier has 53% smaller delay and 58% less power consumption than a regular multiplier.

Original languageEnglish (US)
JournalMaterials Research Society Symposium - Proceedings
Volume626
StatePublished - May 28 2001

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