The problem of selecting a set of paths to optimize the performance of a circuit is studied. The authors assume that gate resizing is the optimizing technique used to reduce the delay of a circuit. That is, during the optimization process the topology of a circuit remains the same and the gate delays are reduced. The objective of the path selection problem is to select as few paths as possible so that when the delays of all selected paths are shortened, the delay of the optimized circuit is guaranteed to meet its performance requirement. The authors first propose an input-vector-oriented path selection algorithm. Due to the fact that the input-vector-oriented algorithm may be not feasible for complex designs with many input pins, they have designed and developed a path-oriented algorithm. For some ISCAS circuits, less than 10% of the long paths are selected by this path-oriented algorithm.