The traditional approach for increasing yield in large memory arrays has been to eliminate all hard errors using repair mechanisms. However, the cost of these mechanisms can become prohibitive for cheaper memories, which have higher error rates. Instead of completely repairing faulty cells, this paper introduces new approximate memory repair mechanisms that only partially repair both CMOS DRAMs and STT-MRAMs. By combining redundant repair with unequal protection, such as skewing the limited spare elements available for repairing faults towards the k most significant bits, and a hybrid bit-shuffling and redundant repair scheme, the new mechanisms maintain excellent output quality while substantially reducing the cost of the repair mechanism, particularly for increasingly important cluster faults.
|Original language||English (US)|
|Title of host publication||Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017|
|Publisher||IEEE Computer Society|
|Number of pages||7|
|State||Published - May 2 2017|
|Event||18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States|
Duration: Mar 14 2017 → Mar 15 2017
|Name||Proceedings - International Symposium on Quality Electronic Design, ISQED|
|Other||18th International Symposium on Quality Electronic Design, ISQED 2017|
|Period||3/14/17 → 3/15/17|
Bibliographical noteFunding Information:
This work was supported in part by C-SPIN, one of six centers supported by the STARnet phase of the Focus Center Research Program (FCRP), a Semiconductor Research Corporation program sponsored by MARCO and DARPA; and by National Science Foundation grant no. CCF-1438286.
© 2017 IEEE.
- Approximate memory repair
- CMOS DRAMs
- unequal protection