Coping with parametric variation at near-threshold voltages

Ulya Karpuzcu, Nam Sung Kim, Josep Torrellas

Research output: Contribution to journalArticlepeer-review

40 Scopus citations


Near-threshold voltage computing (NTC) promises significant improvement in energy efficiency. Unfortunately, when compared to conventional, super-threshold voltage computing (STC), NTC is more sensitive to parametric variation. This results in not only slower and leakier cores, but also substantial speed and power differences between the cores in a many-core chip. NTC's potential cannot be unlocked without addressing the higher impact of variation. To confront variation at the architecture level, the authors introduce a parametric variation model for NTC. They then use the model to show the shortcomings of adapting state-of-the-art STC techniques for variation mitigation to NTC. Finally, they discuss how to tailor variation mitigation to NTC.

Original languageEnglish (US)
Article number6527886
Pages (from-to)6-14
Number of pages9
JournalIEEE Micro
Issue number4
StatePublished - 2013


  • energy and power efficiency
  • multicores
  • near-threshold voltage
  • parameter variation
  • resilience


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