Convex delay models for transistor sizing

Mahesh Ketkar, Kishore Kasamsetty, Sachin Sapatnekar

Research output: Contribution to journalConference articlepeer-review

22 Scopus citations


This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these functions is exploited to accurately model gate delay for modern designs. The delay model is incorporated into a transistor sizing algorithm based on TILOS. The models were characterized by using a set of grid points and then validated using a disjoint data set. The models were found to be within about 10% of SPICE for nearly all of the gate types considered. Also presented are the experimental results of sizing various test circuits.

Original languageEnglish (US)
Pages (from-to)655-660
Number of pages6
JournalProceedings - Design Automation Conference
StatePublished - Jan 1 2000
EventDAC 2000: 37th Design Automation Conference - Los Angeles, CA, USA
Duration: Jun 5 2000Jun 9 2000


Dive into the research topics of 'Convex delay models for transistor sizing'. Together they form a unique fingerprint.

Cite this