TY - JOUR
T1 - Convex delay models for transistor sizing
AU - Ketkar, Mahesh
AU - Kasamsetty, Kishore
AU - Sapatnekar, Sachin
PY - 2000
Y1 - 2000
N2 - This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these functions is exploited to accurately model gate delay for modern designs. The delay model is incorporated into a transistor sizing algorithm based on TILOS. The models were characterized by using a set of grid points and then validated using a disjoint data set. The models were found to be within about 10% of SPICE for nearly all of the gate types considered. Also presented are the experimental results of sizing various test circuits.
AB - This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these functions is exploited to accurately model gate delay for modern designs. The delay model is incorporated into a transistor sizing algorithm based on TILOS. The models were characterized by using a set of grid points and then validated using a disjoint data set. The models were found to be within about 10% of SPICE for nearly all of the gate types considered. Also presented are the experimental results of sizing various test circuits.
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U2 - 10.1145/337292.337607
DO - 10.1145/337292.337607
M3 - Conference article
AN - SCOPUS:0033716234
SN - 0738-100X
SP - 655
EP - 660
JO - Proceedings - Design Automation Conference
JF - Proceedings - Design Automation Conference
T2 - DAC 2000: 37th Design Automation Conference
Y2 - 5 June 2000 through 9 June 2000
ER -