Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs

Nibedita Karmokar; Arvind K Sharma; Jitesh Poojary; Meghna Madhusudan; Ramesh Harjani; Sachin S. Sapatnekar

doi:10.1109/TCAD.2023.3238880

Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs

Nibedita Karmokar, Arvind K Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

7 Scopus citations

Abstract

Process variations and the effect of interconnect parasitics can cause significant perturbations in the performance metrics of capacitive digital-to-analog converters (DACs). This article develops fast constructive procedures for common-centroid placement and routing for binary-weighted and split capacitor array topologies of charge-sharing DACs. Our approach particularly targets FinFET technologies with high wire and via parasitics: in these technology nodes, we show that the switching speed of the capacitor array, as measured by the 3-dB frequency, can be severely degraded by these parasitics, and develop techniques to place and route the capacitor array, for both binary-weighted and split DACs, to optimize the switching speed. A balance between 3-dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.

Original language	English (US)
Pages (from-to)	2782-2795
Number of pages	14
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	42
Issue number	9
DOIs	https://doi.org/10.1109/TCAD.2023.3238880
State	Published - Sep 1 2023

Bibliographical note

Funding Information:
This work was supported in part by the Semiconductor Research Corporation (SRC) and in part by the DARPA IDEA Program (as part of the ALIGN Project through SPAWAR) under Contract N660011824048. This article was recommended by Associate Editor H. E. Graeb

Publisher Copyright:
© 2023 IEEE.

Keywords

Analog circuits
analog layout
capacitor arrays
common-centroid layout
data converters

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10.1109/TCAD.2023.3238880

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@article{812776606ad34c04bf71b748d92e25d7,

title = "Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs",

abstract = "Process variations and the effect of interconnect parasitics can cause significant perturbations in the performance metrics of capacitive digital-to-analog converters (DACs). This article develops fast constructive procedures for common-centroid placement and routing for binary-weighted and split capacitor array topologies of charge-sharing DACs. Our approach particularly targets FinFET technologies with high wire and via parasitics: in these technology nodes, we show that the switching speed of the capacitor array, as measured by the 3-dB frequency, can be severely degraded by these parasitics, and develop techniques to place and route the capacitor array, for both binary-weighted and split DACs, to optimize the switching speed. A balance between 3-dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.",

keywords = "Analog circuits, analog layout, capacitor arrays, common-centroid layout, data converters",

author = "Nibedita Karmokar and Sharma, {Arvind K} and Jitesh Poojary and Meghna Madhusudan and Ramesh Harjani and Sapatnekar, {Sachin S.}",

note = "Funding Information: This work was supported in part by the Semiconductor Research Corporation (SRC) and in part by the DARPA IDEA Program (as part of the ALIGN Project through SPAWAR) under Contract N660011824048. This article was recommended by Associate Editor H. E. Graeb Publisher Copyright: {\textcopyright} 2023 IEEE.",

year = "2023",

month = sep,

day = "1",

doi = "10.1109/TCAD.2023.3238880",

language = "English (US)",

volume = "42",

pages = "2782--2795",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "9",

}

TY - JOUR

T1 - Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs

AU - Karmokar, Nibedita

AU - Sharma, Arvind K

AU - Poojary, Jitesh

AU - Madhusudan, Meghna

AU - Harjani, Ramesh

AU - Sapatnekar, Sachin S.

N1 - Funding Information: This work was supported in part by the Semiconductor Research Corporation (SRC) and in part by the DARPA IDEA Program (as part of the ALIGN Project through SPAWAR) under Contract N660011824048. This article was recommended by Associate Editor H. E. Graeb Publisher Copyright: © 2023 IEEE.

PY - 2023/9/1

Y1 - 2023/9/1

N2 - Process variations and the effect of interconnect parasitics can cause significant perturbations in the performance metrics of capacitive digital-to-analog converters (DACs). This article develops fast constructive procedures for common-centroid placement and routing for binary-weighted and split capacitor array topologies of charge-sharing DACs. Our approach particularly targets FinFET technologies with high wire and via parasitics: in these technology nodes, we show that the switching speed of the capacitor array, as measured by the 3-dB frequency, can be severely degraded by these parasitics, and develop techniques to place and route the capacitor array, for both binary-weighted and split DACs, to optimize the switching speed. A balance between 3-dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.

AB - Process variations and the effect of interconnect parasitics can cause significant perturbations in the performance metrics of capacitive digital-to-analog converters (DACs). This article develops fast constructive procedures for common-centroid placement and routing for binary-weighted and split capacitor array topologies of charge-sharing DACs. Our approach particularly targets FinFET technologies with high wire and via parasitics: in these technology nodes, we show that the switching speed of the capacitor array, as measured by the 3-dB frequency, can be severely degraded by these parasitics, and develop techniques to place and route the capacitor array, for both binary-weighted and split DACs, to optimize the switching speed. A balance between 3-dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.

KW - Analog circuits

KW - analog layout

KW - capacitor arrays

KW - common-centroid layout

KW - data converters

UR - http://www.scopus.com/inward/record.url?scp=85147271147&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85147271147&partnerID=8YFLogxK

U2 - 10.1109/TCAD.2023.3238880

DO - 10.1109/TCAD.2023.3238880

M3 - Article

AN - SCOPUS:85147271147

SN - 0278-0070

VL - 42

SP - 2782

EP - 2795

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 9

ER -

Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs

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