Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients

Arvind K Sharma; Meghna Madhusudan; Steven M. Burns; Soner Yaldiz; Parijat Mukherjee; Ramesh Harjani; Sachin S. Sapatnekar

doi:10.1109/tcad.2024.3402988

Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients

Arvind K Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

The design of active array structures in analog circuits requires careful matching to minimize the impact of variations. This work presents a constructive approach for building these arrays to directly incorporate shifts due to process variations, considering systematic first-order and second order gradients; to account for systematic layout effects, including parasitic mismatch and layout-dependent effects due to stress; and to ensure that the resulting layout delivers high performance. The proposed algorithms are targeted to FinFET technologies and are validated for multiple analog blocks in a commercial 12nm FinFET process. The layouts generated by the proposed method are demonstrated to provide better matching and performance than prior methods.

Original language	English (US)
Pages (from-to)	1
Number of pages	1
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOIs	https://doi.org/10.1109/tcad.2024.3402988
State	Accepted/In press - 2024

Bibliographical note

Publisher Copyright:
IEEE

Keywords

Analog circuits
electromigration
FinFETs
Layout
layout-dependent effects
mismatch
nonlinear gradients
Routing
routing parasitic
Systematics
Transistors
Wires

Publisher link

10.1109/tcad.2024.3402988

Cite this

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title = "Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients",

abstract = "The design of active array structures in analog circuits requires careful matching to minimize the impact of variations. This work presents a constructive approach for building these arrays to directly incorporate shifts due to process variations, considering systematic first-order and second order gradients; to account for systematic layout effects, including parasitic mismatch and layout-dependent effects due to stress; and to ensure that the resulting layout delivers high performance. The proposed algorithms are targeted to FinFET technologies and are validated for multiple analog blocks in a commercial 12nm FinFET process. The layouts generated by the proposed method are demonstrated to provide better matching and performance than prior methods.",

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AU - Yaldiz, Soner

AU - Mukherjee, Parijat

AU - Harjani, Ramesh

AU - Sapatnekar, Sachin S.

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KW - FinFETs

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KW - Transistors

KW - Wires

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Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients

Abstract

Bibliographical note

Keywords

Publisher link

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