Abstract
The accuracy and linearity of capacitive digital-to-analog converters (DACs) depend on precise capacitor ratios, but these ratios are perturbed by process variations and parasitics. This paper develops fast constructive procedures for common-centroid placement and routing for binary-weighted capacitors in charge-sharing DACs. Parasitics also degrade the switching speed of a capacitor array, particularly in FinFET nodes with severe wire/via resistances. To overcome this, the capacitor array is placed and routed to optimize switching speed, measured by the 3dB frequency. A balance between 3dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.
Original language | English (US) |
---|---|
Title of host publication | Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 |
Editors | Cristiana Bolchini, Ingrid Verbauwhede, Ioana Vatajelu |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 166-171 |
Number of pages | 6 |
ISBN (Electronic) | 9783981926361 |
DOIs | |
State | Published - 2022 |
Event | 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 - Virtual, Online, Belgium Duration: Mar 14 2022 → Mar 23 2022 |
Publication series
Name | Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 |
---|
Conference
Conference | 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 |
---|---|
Country/Territory | Belgium |
City | Virtual, Online |
Period | 3/14/22 → 3/23/22 |
Bibliographical note
Funding Information:This work is supported in part by the DARPA IDEA program, as part of the ALIGN project, under SPAWAR Contract N660011824048.
Publisher Copyright:
© 2022 EDAA.