Confidence scalable post-silicon statistical delay prediction under process variations

Liu Qunzeng, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Scopus citations

Abstract

Due to increased variability trends in nanoscale integrated circuits, statistical circuit analysis has become essential. We present a novel method for post-silicon analysis that gathers data from a small number of on-chip test structures, and combines this information with pre-silicon statistical timing analysis to obtain narrow, die-specific, timing PDFs. Experimental results show that for the benchmark suite being considered, taking all parameter variations into consideration, our approach can get a PDF with the standard deviation 83.5% smaller on average than the SSTA result. The approach is scalable to smaller test structure overheads.

Original languageEnglish (US)
Title of host publication2007 44th ACM/IEEE Design Automation Conference, DAC'07
Pages497-502
Number of pages6
DOIs
StatePublished - 2007
Event2007 44th ACM/IEEE Design Automation Conference, DAC'07 - San Diego, CA, United States
Duration: Jun 4 2007Jun 8 2007

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other2007 44th ACM/IEEE Design Automation Conference, DAC'07
CountryUnited States
CitySan Diego, CA
Period6/4/076/8/07

Keywords

  • Post-silicon optimization
  • Statistical timing analysis

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