Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs

Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

A method for concurrent transistor sizing and buffer insertion is proposed. The method considers the tradeoff between upsizing transistors and inserting buffers and chooses the solution with the lowest possible power and area cost. The method operates by analyzing the feasible region of the cost-delay curves of the unbuffered and buffered circuits. As such the feasible region of circuits optimized by our method is extended to encompass the envelop of cost-delay curves which represent the union of the feasible regions of all buffered and unbuffered versions of the circuit. The method is efficient and tunable in that optimality can be traded for compute time and the method can in theory produce near optimal results.

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Physical Design
Pages130-135
Number of pages6
StatePublished - Jan 1 1997
EventProceedings of the 1997 1st International Symposium on Physical Design, ISPD - Napa Valley, CA, USA
Duration: Apr 14 1997Apr 16 1997

Other

OtherProceedings of the 1997 1st International Symposium on Physical Design, ISPD
CityNapa Valley, CA, USA
Period4/14/974/16/97

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