Computer arithmetic architectures with redundant number systems

Hosahalli R. Srinivas, Keshab K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations


Redundant arithmetic number systems are gaining popularity in computationally intensive environments particularly because of the carry-free addition/subtraction properties they possess. This property has enabled arithmetic operations such as addition, multiplication, division, square root, etc., to be performed much faster than with conventional binary number systems. In this paper, some of the recent contributions to the area of design of redundant arithmetic based addition, multiplication, division, and square root algorithms and architectures are briefly discussed. Also, only the use of bit/digit-parallel implementation for architectures is discussed so that the enhancement in speed through the use of redundant arithmetic becomes immediately apparent as opposed to the use of bit/digit-serial architectures, where the primary justi-ficationfor their use is to conserve area. A new radix 2 division algorithm using over-redundant radix 2 quotient digits and requiring a 2 digit quotient selection function is also presented.

Original languageEnglish (US)
Title of host publicationConference Record - 28th Asilomar Conference on Signals, Systems and Computers, ACSSC 1994
PublisherIEEE Computer Society
Number of pages5
ISBN (Electronic)0818664053
StatePublished - 1994
Event28th Asilomar Conference on Signals, Systems and Computers, ACSSC 1994 - Pacific Grove, United States
Duration: Oct 31 1994Nov 2 1994

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)1058-6393


Conference28th Asilomar Conference on Signals, Systems and Computers, ACSSC 1994
Country/TerritoryUnited States
CityPacific Grove

Bibliographical note

Funding Information:
'This research was supported by the Office of Naval Research under contract number N00014-91-5-1008.

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