TY - JOUR
T1 - Complexity reduction of the decoders for interleaved trellis coded modulation schemes for 10 Gigabit Ethernet over copper
AU - Gu, Yongru
AU - Parhi, Keshab K
PY - 2004
Y1 - 2004
N2 - 10GBASE-T (10 Gigabit Ethernet over unshielded twisted pairs) will probably use a 10-level pulse amplitude modulation (PAM10) as well as a 4D trellis code similar to the one in 1000BASE-T (1000 Megabit Ethernet over copper medium). The trellis code can be used in a conventional way as in 1000BASE-T but the corresponding decoder with a long critical path needs to operate at 833MHz. To solve the problem, two interleaved trellis coded modulation schemes were proposed in our previous work. The inherent decoding speed requirements can be relaxed by factors of 4 and 2, respectively. Due to intersymbol interference (ISI), the branch metric units in the decoders corresponding to the two interleaved modulation schemes are much more complicated than that in the conventional decoder. Thus this paper considers the problem of complexity reduction of the decoders for the two interleaved modulation schemes. Two complexity reduction schemes are proposed. Simulation results show that the performance loss due to complexity reduction is negligible.
AB - 10GBASE-T (10 Gigabit Ethernet over unshielded twisted pairs) will probably use a 10-level pulse amplitude modulation (PAM10) as well as a 4D trellis code similar to the one in 1000BASE-T (1000 Megabit Ethernet over copper medium). The trellis code can be used in a conventional way as in 1000BASE-T but the corresponding decoder with a long critical path needs to operate at 833MHz. To solve the problem, two interleaved trellis coded modulation schemes were proposed in our previous work. The inherent decoding speed requirements can be relaxed by factors of 4 and 2, respectively. Due to intersymbol interference (ISI), the branch metric units in the decoders corresponding to the two interleaved modulation schemes are much more complicated than that in the conventional decoder. Thus this paper considers the problem of complexity reduction of the decoders for the two interleaved modulation schemes. Two complexity reduction schemes are proposed. Simulation results show that the performance loss due to complexity reduction is negligible.
UR - https://www.scopus.com/pages/publications/17044365451
UR - https://www.scopus.com/pages/publications/17044365451#tab=citedBy
M3 - Conference article
AN - SCOPUS:17044365451
SN - 1520-6130
SP - 130
EP - 135
JO - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
JF - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
T2 - 2004 IEEE Workshop on Signal Processing Systems Design and Implementation, Proceedings
Y2 - 13 October 2004 through 15 October 2004
ER -