Complementary n- and p-type TFETs on the same InAs/Al0.05Ga 0.95Sb platform

E. Baravelli; E. Gnani; R. Grassi; A. Gnudi; S. Reggiani; G. Baccarani

doi:10.1109/ESSDERC.2013.6818821

Complementary n- and p-type TFETs on the same InAs/Al_0.05Ga _0.95Sb platform

E. Baravelli, E. Gnani, R. Grassi, A. Gnudi, S. Reggiani, G. Baccarani

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

Design of complementary n- and p-type heterojunction tunnel field-effect transistors (TFETs) realized with the same InAs/Al_0.05Ga _0.95Sb material pair is carried out in this work using 3D, full-quantum simulations. Several design parameters are optimized, leading to a TFET pair with similar dimensions and feasible aspect ratios, which exhibit average subthreshold slopes around 30 mV/dec and relatively high on-currents of 280 (n-TFET) and 165 μA/ μm (p-TFET) at 0.4 V supply voltage. This is combined with low operating power (LOP) compatible off-currents, which makes the proposed technology platform well suited for LOP applications and even usable in HP scenarios. Devices with reduced cross section (7 nm instead of 10 nm) are also proposed as good candidates for low standby power (LSTP) scenarios.

Original language	English (US)
Title of host publication	ESSDERC 2013 - Proceedings of the 43rd European Solid-State Device Research Conference
Publisher	IEEE Computer Society
Pages	69-72
Number of pages	4
ISBN (Print)	9781479906499
DOIs	https://doi.org/10.1109/ESSDERC.2013.6818821
State	Published - 2013
Event	43rd European Solid-State Device Research Conference, ESSDERC 2013 - Bucharest, Romania Duration: Sep 16 2013 → Sep 20 2013

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Conference

Conference	43rd European Solid-State Device Research Conference, ESSDERC 2013
Country/Territory	Romania
City	Bucharest
Period	9/16/13 → 9/20/13

Publisher link

10.1109/ESSDERC.2013.6818821

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Cite this

Baravelli, E., Gnani, E., Grassi, R., Gnudi, A., Reggiani, S., & Baccarani, G. (2013). Complementary n- and p-type TFETs on the same InAs/Al_0.05Ga _0.95Sb platform. In ESSDERC 2013 - Proceedings of the 43rd European Solid-State Device Research Conference (pp. 69-72). Article 6818821 (European Solid-State Device Research Conference). IEEE Computer Society. https://doi.org/10.1109/ESSDERC.2013.6818821

Complementary n- and p-type TFETs on the same InAs/Al_0.05Ga _0.95Sb platform. / Baravelli, E.; Gnani, E.; Grassi, R. et al.
ESSDERC 2013 - Proceedings of the 43rd European Solid-State Device Research Conference. IEEE Computer Society, 2013. p. 69-72 6818821 (European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Baravelli, E, Gnani, E, Grassi, R, Gnudi, A, Reggiani, S & Baccarani, G 2013, Complementary n- and p-type TFETs on the same InAs/Al_0.05Ga _0.95Sb platform. in ESSDERC 2013 - Proceedings of the 43rd European Solid-State Device Research Conference., 6818821, European Solid-State Device Research Conference, IEEE Computer Society, pp. 69-72, 43rd European Solid-State Device Research Conference, ESSDERC 2013, Bucharest, Romania, 9/16/13. https://doi.org/10.1109/ESSDERC.2013.6818821

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abstract = "Design of complementary n- and p-type heterojunction tunnel field-effect transistors (TFETs) realized with the same InAs/Al0.05Ga 0.95Sb material pair is carried out in this work using 3D, full-quantum simulations. Several design parameters are optimized, leading to a TFET pair with similar dimensions and feasible aspect ratios, which exhibit average subthreshold slopes around 30 mV/dec and relatively high on-currents of 280 (n-TFET) and 165 μA/ μm (p-TFET) at 0.4 V supply voltage. This is combined with low operating power (LOP) compatible off-currents, which makes the proposed technology platform well suited for LOP applications and even usable in HP scenarios. Devices with reduced cross section (7 nm instead of 10 nm) are also proposed as good candidates for low standby power (LSTP) scenarios.",

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AB - Design of complementary n- and p-type heterojunction tunnel field-effect transistors (TFETs) realized with the same InAs/Al0.05Ga 0.95Sb material pair is carried out in this work using 3D, full-quantum simulations. Several design parameters are optimized, leading to a TFET pair with similar dimensions and feasible aspect ratios, which exhibit average subthreshold slopes around 30 mV/dec and relatively high on-currents of 280 (n-TFET) and 165 μA/ μm (p-TFET) at 0.4 V supply voltage. This is combined with low operating power (LOP) compatible off-currents, which makes the proposed technology platform well suited for LOP applications and even usable in HP scenarios. Devices with reduced cross section (7 nm instead of 10 nm) are also proposed as good candidates for low standby power (LSTP) scenarios.

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