Complementary III-V heterostructure FETs for low power integrated circuits

A. I. Akinwande; P. P. Ruden; D. E. Grider; J. C. Nohava; T. E. Nohava; P. D. Joslyn; J. E. Breezley

Complementary III-V heterostructure FETs for low power integrated circuits

A. I. Akinwande, P. P. Ruden, D. E. Grider, J. C. Nohava, T. E. Nohava, P. D. Joslyn, J. E. Breezley

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

13 Scopus citations

Abstract

The authors report on a complementary III-V heterostructure FET (HFET) technology that makes use of high AlAs mole fraction (Al,Ga)As barrier layers to reduce the gate leakage currents of n- and p-channel heterostructure FETs. The subthreshold currents and drain-to-gate leakage currents of p-HFETs are also substantially reduced as a result of the high AlAs mole fraction (Al,Ga)As barrier layer. A 1024 × 1 bit complementary HFET SRAM with access times as low as 4.6 ns and power dissipation of 34.8 mW has also been demonstrated using this technology.

Original language	English (US)
Pages (from-to)	983-986
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
State	Published - Dec 1 1990
Event	1990 International Electron Devices Meeting - San Francisco, CA, USA Duration: Dec 9 1990 → Dec 12 1990

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title = "Complementary III-V heterostructure FETs for low power integrated circuits",

abstract = "The authors report on a complementary III-V heterostructure FET (HFET) technology that makes use of high AlAs mole fraction (Al,Ga)As barrier layers to reduce the gate leakage currents of n- and p-channel heterostructure FETs. The subthreshold currents and drain-to-gate leakage currents of p-HFETs are also substantially reduced as a result of the high AlAs mole fraction (Al,Ga)As barrier layer. A 1024 × 1 bit complementary HFET SRAM with access times as low as 4.6 ns and power dissipation of 34.8 mW has also been demonstrated using this technology.",

author = "Akinwande, {A. I.} and Ruden, {P. P.} and Grider, {D. E.} and Nohava, {J. C.} and Nohava, {T. E.} and Joslyn, {P. D.} and Breezley, {J. E.}",

year = "1990",

month = dec,

day = "1",

language = "English (US)",

pages = "983--986",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

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note = "1990 International Electron Devices Meeting ; Conference date: 09-12-1990 Through 12-12-1990",

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TY - JOUR

T1 - Complementary III-V heterostructure FETs for low power integrated circuits

AU - Akinwande, A. I.

AU - Ruden, P. P.

AU - Grider, D. E.

AU - Nohava, J. C.

AU - Nohava, T. E.

AU - Joslyn, P. D.

AU - Breezley, J. E.

PY - 1990/12/1

Y1 - 1990/12/1

N2 - The authors report on a complementary III-V heterostructure FET (HFET) technology that makes use of high AlAs mole fraction (Al,Ga)As barrier layers to reduce the gate leakage currents of n- and p-channel heterostructure FETs. The subthreshold currents and drain-to-gate leakage currents of p-HFETs are also substantially reduced as a result of the high AlAs mole fraction (Al,Ga)As barrier layer. A 1024 × 1 bit complementary HFET SRAM with access times as low as 4.6 ns and power dissipation of 34.8 mW has also been demonstrated using this technology.

AB - The authors report on a complementary III-V heterostructure FET (HFET) technology that makes use of high AlAs mole fraction (Al,Ga)As barrier layers to reduce the gate leakage currents of n- and p-channel heterostructure FETs. The subthreshold currents and drain-to-gate leakage currents of p-HFETs are also substantially reduced as a result of the high AlAs mole fraction (Al,Ga)As barrier layer. A 1024 × 1 bit complementary HFET SRAM with access times as low as 4.6 ns and power dissipation of 34.8 mW has also been demonstrated using this technology.

UR - http://www.scopus.com/inward/record.url?scp=0025575813&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025575813&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0025575813

SN - 0163-1918

SP - 983

EP - 986

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - 1990 International Electron Devices Meeting

Y2 - 9 December 1990 through 12 December 1990

ER -

Complementary III-V heterostructure FETs for low power integrated circuits

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