Complementary III-V heterostructure FETs for low power integrated circuits

A. I. Akinwande, P. P. Ruden, D. E. Grider, J. C. Nohava, T. E. Nohava, P. D. Joslyn, J. E. Breezley

Research output: Contribution to journalConference articlepeer-review

13 Scopus citations


The authors report on a complementary III-V heterostructure FET (HFET) technology that makes use of high AlAs mole fraction (Al,Ga)As barrier layers to reduce the gate leakage currents of n- and p-channel heterostructure FETs. The subthreshold currents and drain-to-gate leakage currents of p-HFETs are also substantially reduced as a result of the high AlAs mole fraction (Al,Ga)As barrier layer. A 1024 × 1 bit complementary HFET SRAM with access times as low as 4.6 ns and power dissipation of 34.8 mW has also been demonstrated using this technology.

Original languageEnglish (US)
Pages (from-to)983-986
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - Dec 1 1990
Event1990 International Electron Devices Meeting - San Francisco, CA, USA
Duration: Dec 9 1990Dec 12 1990


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