Comparing simulation techniques for microarchitecture-aware floorplanning

Keyphrases

• Microarchitecture 100%
• Floorplanning 100%
• Simulation Techniques 100%
• Reduced Inputs 40%
• System Performance 20%
• Performance Improvement 20%
• Latency 20%
• Process Optimization 20%
• Flip-flop 20%
• Technology Node 20%
• Microprocessor 20%
• Statistical Sampling 20%
• Simulation Time 20%
• Nanometer Technology 20%
• Performance Bottleneck 20%
• Absolute Accuracy 20%
• Relative Ordering 20%
• Global Placement 20%
• Cycle-accurate Simulation 20%
• Reference Input 20%
• System Buses 20%
• Physical Design 20%
• Discrete Optimization Problems 20%
• Set Sampling 20%

Computer Science

• Simulation Mode 100%
• Microarchitecture 100%
• Floorplanning 100%
• Optimization Problem 20%
• Pipelining 20%
• Speed-up 20%
• Systems Performance 20%
• Physical Design 20%
• Performance Bottleneck 20%
• Global Placement 20%
• Discrete Optimization 20%
• Performance Improvement 20%
• Simulation Time 20%
• Criticality 20%
• Microprocessor 20%
• Input Reference 20%