Compact modeling and simulation of accelerated circuit aging

Devyani Patra; Jiayang Zhang; Runsheng Wang; Mehdi Katoozi; Ethan H. Cannon; Ru Huang; Yu Cao

doi:10.1109/CICC.2018.8357063

Compact modeling and simulation of accelerated circuit aging

Devyani Patra, Jiayang Zhang, Runsheng Wang, Mehdi Katoozi, Ethan H. Cannon, Ru Huang, Yu Cao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

Accelerated aging becomes progressively pronounced in various circuits, due to the feedback between circuit operation and aging effects, especially HCI. To predict this behavior, the conventional method requires iterative simulations to track the elevated degradation rate, which is expensive in computation. In this paper, a compact model is derived for accelerated aging. By analyzing the underlying mechanism, the new model connects the degradation rate with both reliability physics and circuit topology. It is compatible with circuit simulation, general for design conditions, and efficient in long-term prediction. The new model is validated by silicon data at 65nm, 28nm, and 16/14nm technologies, demonstrating its scalability and effectiveness. Furthermore, it is applied to several benchmark circuits to illustrate the importance of accelerated aging.

Original language	English (US)
Title of host publication	2018 IEEE Custom Integrated Circuits Conference, CICC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-4
Number of pages	4
ISBN (Electronic)	9781538624838
DOIs	https://doi.org/10.1109/CICC.2018.8357063
State	Published - May 9 2018
Externally published	Yes
Event	2018 IEEE Custom Integrated Circuits Conference, CICC 2018 - San Diego, United States Duration: Apr 8 2018 → Apr 11 2018

Publication series

Name	2018 IEEE Custom Integrated Circuits Conference, CICC 2018

Other

Other	2018 IEEE Custom Integrated Circuits Conference, CICC 2018
Country/Territory	United States
City	San Diego
Period	4/8/18 → 4/11/18

Bibliographical note

Funding Information:
VI. ACKNOWLEDGEMENT This work was supported in part by DARPA contract HR0011-16-C-0041. The views, opinions, and/or findings expressed are those of the author(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government. VII. REFERENCES

Publisher Copyright:
© 2018 IEEE.

Publisher link

10.1109/CICC.2018.8357063

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Patra, D., Zhang, J., Wang, R., Katoozi, M., Cannon, E. H., Huang, R., & Cao, Y. (2018). Compact modeling and simulation of accelerated circuit aging. In 2018 IEEE Custom Integrated Circuits Conference, CICC 2018 (pp. 1-4). (2018 IEEE Custom Integrated Circuits Conference, CICC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2018.8357063

Compact modeling and simulation of accelerated circuit aging. / Patra, Devyani; Zhang, Jiayang; Wang, Runsheng et al.
2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4 (2018 IEEE Custom Integrated Circuits Conference, CICC 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Patra, D, Zhang, J, Wang, R, Katoozi, M, Cannon, EH, Huang, R & Cao, Y 2018, Compact modeling and simulation of accelerated circuit aging. in 2018 IEEE Custom Integrated Circuits Conference, CICC 2018. 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, San Diego, United States, 4/8/18. https://doi.org/10.1109/CICC.2018.8357063

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N2 - Accelerated aging becomes progressively pronounced in various circuits, due to the feedback between circuit operation and aging effects, especially HCI. To predict this behavior, the conventional method requires iterative simulations to track the elevated degradation rate, which is expensive in computation. In this paper, a compact model is derived for accelerated aging. By analyzing the underlying mechanism, the new model connects the degradation rate with both reliability physics and circuit topology. It is compatible with circuit simulation, general for design conditions, and efficient in long-term prediction. The new model is validated by silicon data at 65nm, 28nm, and 16/14nm technologies, demonstrating its scalability and effectiveness. Furthermore, it is applied to several benchmark circuits to illustrate the importance of accelerated aging.

AB - Accelerated aging becomes progressively pronounced in various circuits, due to the feedback between circuit operation and aging effects, especially HCI. To predict this behavior, the conventional method requires iterative simulations to track the elevated degradation rate, which is expensive in computation. In this paper, a compact model is derived for accelerated aging. By analyzing the underlying mechanism, the new model connects the degradation rate with both reliability physics and circuit topology. It is compatible with circuit simulation, general for design conditions, and efficient in long-term prediction. The new model is validated by silicon data at 65nm, 28nm, and 16/14nm technologies, demonstrating its scalability and effectiveness. Furthermore, it is applied to several benchmark circuits to illustrate the importance of accelerated aging.

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Compact modeling and simulation of accelerated circuit aging

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