Compact model of carbon nanotube transistor and interconnect

Saurabh Sinha, Asha Balijepalli, Yu Cao

Research output: Contribution to journalArticlepeer-review

21 Scopus citations

Abstract

A noniterative physics-based compact model is developed for carbon nanotube (CNT) transistor and interconnect in order to support early stage design exploration. Based on the derivation of surface potential, the new model accurately predicts both IV and CV characteristics. It is scalable to key process and design parameters, such as the diameter, chirality, contact materials, gate dielectrics, and bias voltages. Without any iteration in model computation, the proposed model significantly enhances the simulation efficiency for large-scale design research. By benchmarking circuit performance, the optimal space of the CNT process is further localized. It is observed that for a Schottky-barrier CNT transistor with the diameter range of 1-1.5 nm, the circuit can be more than 8 × faster than that of 22-nm CMOS, with the tolerance to the variation in contact materials.

Original languageEnglish (US)
Pages (from-to)2232-2242
Number of pages11
JournalIEEE Transactions on Electron Devices
Volume56
Issue number10
DOIs
StatePublished - 2009
Externally publishedYes

Bibliographical note

Funding Information:
The authors would like to thank the Materials, Structure, and Devices Center and also the Center of Circuits and System Solutions, two of the five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program, for their support. The authors would also like to thank J. Deng and H.-S. P. Wong of Stanford University for their support and the discussions.

Keywords

  • Carbon nanotube (CNT)
  • Interconnect
  • Modeling
  • Optimum delay
  • Process variations
  • Schottky barrier (SB)
  • Surface potential

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