Combining hardware and software cache coherence strategies

David J. Lilja, Pen Chung Yew

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations


Efficiently maintaining cache coherence is a major problem in large-scale shared memory multiprocessors. Hardware directory schemes have very high memory requirements, while software-directed schemes must rely on imprecise compile-time memory disambiguation. Recently proposed dynamic directory schemes allocate pointers to blocks only as they are referenced, which significantly reduces their memory requirements, but they still allocate pointers to blocks that do not need them. We show how compiler marking can further reduce the directory size by allocating pointers only when necessary. Using trace-driven simulations, we find that the performance of this new approach is comparable to other coherence schemes, but with significantly lower memory requirements.

Original languageEnglish (US)
Title of host publicationICS 1991 - Proceedings of the 5th International Conference on Supercomputing
EditorsEdward S. Davidson, Friedel Hossfield
PublisherAssociation for Computing Machinery
Number of pages10
ISBN (Print)0897914341, 9780897914345
StatePublished - Jun 1 1991
Externally publishedYes
Event5th International Conference on Supercomputing, ICS 1991 - Cologne, Germany
Duration: Jun 17 1991Jun 21 1991

Publication series

NameProceedings of the International Conference on Supercomputing


Other5th International Conference on Supercomputing, ICS 1991

Bibliographical note

Funding Information:
This work was supported by the National Science Foundation under Grant No. NSF MIP-S41011O, with additional support from NASA Ames Research Center Grant No. NASA NCC 2-559 (DARPA), National Science Foundation Grant No. NSF MIP-88-07775, and Department of Energy Grant No. DOE DEFG02-85ER25001. David Lilja also is supported by a DARPA/NASA Assistantship in Parallel Processing.

Publisher Copyright:
© 1991 ACM.


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